1. Field of the Invention
The present invention generally relates to methods and apparatus for testing digital electronic circuit designs and more particularly employing techniques for selection of test cases for use on simulated logic designs to improve efficiency of test operation.
2. Description of the Prior Art
The earliest digital circuit designs were constructed in prototype form and tested using actual electronic inputs and outputs. Errors measured using this process were then physically corrected in the prototype and the system retested electronically. This approach is suitable only for the simplest of designs and becomes increasingly more costly to employ with increasing design complexity. Furthermore, it is questionable whether this approach could even be implemented with the highly integrated nature of current designs.
The current approaches tend to be based upon simulation of a digital circuit design. According to this technique, software tools are utilized to simulate the structure and operation of a logic circuit. Should an error be found, a design change can be made through a simple change to the simulation data base. After the design is finalized, other software tools can automatically or semi-automatically document the circuit design and assist in implementation with a plotter or other output device. Because finalized designs are typically stored for future use, complete designs and portions thereof can be easily referenced for use in future designs. As a result, commonly used components (e.g., registers, accumulators, etc.) are saved within readily accessible libraries. In this way, very complex circuits can be designed with a minimal amount of effort.
With the widespread use of such software design tools (i.e., simulators, etc.), a key problem becomes testing of the simulated design. Testing of so-called combinational logic is relatively straightforward. However, virtually all designs which are commercially useful have various sequential state saving elements (e.g., flip-flops, registers, etc.). The most complex of current designs, such as instruction processors, having literally tens of thousands of gates are substantially more complex than simple logic trees. Thus, testing of such designs is a formidable problem.
The design of tests to determine proper operation of a simulated or emulated design becomes a major design problem in itself. At the highest level, manual design of test conditions tends to be relatively expensive to prepare, because of the engineering time involved, but relatively efficient to run, because the intelligence employed in the test design tends to focus on the most significant test cases.
Totally random tests, on the other hand, tend to be inexpensive to develop, because of the automatic preparation, but relatively inefficient to run, because truly random tests tend to employ many test cases which correspond to a single logic error. Whether randomly or manually generated, many test cases which point to the same logic error tend to waste simulation run time and error result analysis time because of these redundant test case.